--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 10.1.03
--  \   \         Application : xaw2vhdl
--  /   /         Filename : clock_synthesis.vhd
-- /___/   /\     Timestamp : 02/19/2009 21:13:55
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: xaw2vhdl-st C:\hans\rekonstrukt\ise\\clock_synthesis.xaw C:\hans\rekonstrukt\ise\\clock_synthesis
--Design Name: clock_synthesis
--Device: xc3s500e-5fg320
--
-- Module clock_synthesis
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;

entity clock_synthesis is
  port (CLKIN_IN        : in  std_logic;
        CLKDV_OUT       : out std_logic;
        LOCKED_OUT      : out std_logic);
end clock_synthesis;

architecture BEHAVIORAL of clock_synthesis is
  signal CLKDV_BUF   : std_logic;
  signal CLKFB_IN    : std_logic;
  signal CLKIN_IBUFG : std_logic;
  signal CLK0_BUF    : std_logic;
  signal GND_BIT     : std_logic;
begin
  GND_BIT         <= '0';
  CLKDV_BUFG_INST : BUFG
    port map (I => CLKDV_BUF,
              O => CLKDV_OUT);

  CLKIN_IBUFG_INST : IBUFG
    port map (I => CLKIN_IN,
              O => CLKIN_IBUFG);

  CLK0_BUFG_INST : BUFG
    port map (I => CLK0_BUF,
              O => CLKFB_IN);

  DCM_SP_INST : DCM_SP
    generic map(CLK_FEEDBACK          => "1X",
                CLKDV_DIVIDE          => 2.0,
                CLKFX_DIVIDE          => 1,
                CLKFX_MULTIPLY        => 4,
                CLKIN_DIVIDE_BY_2     => false,
                CLKIN_PERIOD          => 20.000,
                CLKOUT_PHASE_SHIFT    => "NONE",
                DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",
                DFS_FREQUENCY_MODE    => "LOW",
                DLL_FREQUENCY_MODE    => "LOW",
                DUTY_CYCLE_CORRECTION => true,
                FACTORY_JF            => x"C080",
                PHASE_SHIFT           => 0,
                STARTUP_WAIT          => false)
    port map (CLKFB    => CLKFB_IN,
              CLKIN    => CLKIN_IBUFG,
              DSSEN    => GND_BIT,
              PSCLK    => GND_BIT,
              PSEN     => GND_BIT,
              PSINCDEC => GND_BIT,
              RST      => GND_BIT,
              CLKDV    => CLKDV_BUF,
              CLKFX    => open,
              CLKFX180 => open,
              CLK0     => CLK0_BUF,
              CLK2X    => open,
              CLK2X180 => open,
              CLK90    => open,
              CLK180   => open,
              CLK270   => open,
              LOCKED   => LOCKED_OUT,
              PSDONE   => open,
              STATUS   => open);

end BEHAVIORAL;


